CMOS thin-film transistor having split gate structure
US5528056A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 1995 |
| Grant date | Jun 18, 1996 |
| Priority date | — |
| Expiry date | Feb 22, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/00
Abstract
A thin-film semiconductor device having a CMOS inverter comprising a pair of n-type and p-type thin-film transistors, wherein the gate electrode of at least one of the paired thin-film transistors comprises a plurality of gate electrode sections spaced apart along the channel length. The channel region of the n-type thin-film transistor is doped with p-type impurities. This structure serves to reduce the leakage current and maintain high OFF resistance for a high source-drain voltage. Further, since a good symmetry of characteristics is maintained between the n-type and p-type thin-film transistors that constitute the CMOS inverter, no appreciable bias is caused in the output voltage of the CMOS inverter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.