CMOS strobed comparator with programmable hysteresis
US5528185A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 1995 |
| Grant date | Jun 18, 1996 |
| Priority date | — |
| Expiry date | Feb 13, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/3565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A comparator produces a digital output based upon a differential input signal and hysteresis. To inject positive feedback, a second differential pair is added. This feedback pair is nominally identical to the input pair. If the comparator has recently sensed a positive input of sufficient magnitude to drive the comparator output high, switches are turned on coupling a positive hysteresis voltage to the inputs of the feedback differential pair. By coupling a fixed current differential from the second differential pair to the input differential pair, the effective switching threshold of the comparator is changed. A non-overlapping clock generator is formed so that the switches will not turn on simultaneously so as to short the hysteresis reference voltage source. The hysteresis voltage source can be centered at any voltage that does not exceed the common mode range of the input pair. In a first alternative embodiment, the ratio of feedback is not unity, such that the hysteresis voltage is linearly related to the noise margin. In a second alternative embodiment, a more complicated switch matrix can be used to provide a variety of different hysteresis voltage levels. By including a mor…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.