5-volt tolerant bi-directional i/o pad for 3-volt-optimized integrated circuits
US5528447A · kind A · utility
23Cited by
1References
8Claims
0Family size
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Key dates
| Filing date | Sep 30, 1994 |
| Grant date | Jun 18, 1996 |
| Priority date | — |
| Expiry date | Sep 30, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In an electronic IC package, an I/O PAD circuit design which protects 3 Volt optimized I/O functional circuits from damage due to the application of external 5 Volt signals to the I/O PAD both while the functional circuit design is powered on and powered off. When the I/O circuits associated with the I/O PAD are powered on, the present invention protects the I/O circuits by applying well known designs. However, when the I/O circuits associated with the I/O PAD are powered off, the present invention draws power from the external 5 Volt signal to activate additional transistors to protect the powered off I/O circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.