Programmable high performance data communication adapter for high speed packet transmission networks
US5528587A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 1994 |
| Grant date | Jun 18, 1996 |
| Priority date | — |
| Expiry date | Jun 1, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9068
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprises PA1 means for buffering (132) said data packets, PA1 means for identifying said buffering means and said data packets in said buffering means, PA1 means for queueing (FIG. 15) in storing means (131) said identifying means in a single instruction, PA1 means for dequeueing (FIG. 16) from said storing (131) means said identifying means in another single instruction, PA1 means for releasing said buffering means, Each instruction comprises up to three operations executed in parallel by said processing means: PA1 an arithmetical and logical (ALU) operation on said identifying means, PA1 memory operation on said storing means, and PA1 a sequence operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.