Bus driver/receiver circuitry and systems and methods using the same
US5530392A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 1995 |
| Grant date | Jun 25, 1996 |
| Priority date | — |
| Expiry date | Apr 11, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35606
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Data transmission circuitry 200 is disclosed which includes a transmission line 201, driver circuitry 202, and receiver circuitry 206. Driver circuitry 202 is coupled to transmission line 201 and sets transmission line 201 to a low transmission voltage level during transmission of information of a first logic state and sets transmission line 201 to a higher transmission voltage during transmission of information of a second logic state. Receiver circuitry 206 compares the voltage on transmission line 201 with a static reference voltage which is a predetermined fraction of the higher transmission voltage and in response latches an output to a corresponding logic state. Receiver circuitry 206 latches the output in an output high logic state to an output voltage which is a multiple of the higher transmission voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.