CMOS circuit with increased breakdown strength

US5530394A · kind A · utility

Assignee

• Deutsche ITT Industries, GmbH · DE

Inventors

• Lothar Blossfeld · Glückstadt, DE
• Ulrich Theus · Gundelfingen, DE
• Mario Motz · Wernberg, AT

Key dates

• Filing date: Oct 5, 1994
• Grant date: Jun 25, 1996
• Expiry date: Oct 5, 2014

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

In a CMOS circuit having at least a first subcircuit coupled between a first point of potential and a first circuit node, and having a second subcircuit coupled between a second circuit node and a second point of potential, said first and second circuit nodes being coupled together, the improvement in combination therewith, comprising: first circuit means coupled to the first point of potential for converting the first potential to a third potential as a function of the magnitude of said first potential, said third potential being of a value inbetween the first and second potentials; a FET having source, drain, gate and well terminals, said source terminal being coupled to said well terminal and to said first circuit node, said third potential being applied to said gate terminal, said drain terminal being coupled to said second circuit node; wherein said FET, in conjunction with said first circuit means, operates to selectively provide a difference in potential between said first and second circuit nodes, thereby preventing voltage breakdown within said subcircuits.