Reference voltage generating circuit of semiconductor memory device
US5530397A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 1994 |
| Grant date | Jun 25, 1996 |
| Priority date | — |
| Expiry date | Jul 27, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/147
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reference voltage generating circuit of a DRAM includes a current mirror circuit constituted of first to fourth transistors. The gate of the third transistor is connected to the source of a fifth transistor. When a zero-power on reset signal, which becomes L on turn-on of the power supply, and becomes H after a predetermined period, is applied to the gate of the fifth transistor, and an external power supply voltage is forced to be applied to the gate of the third transistor on turn-on of the power supply, a reference voltage following the rise of the external power supply voltage is provided from the output of the current mirror circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.