Image memory control device
US5530458A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 28, 1994 |
| Grant date | Jun 25, 1996 |
| Priority date | — |
| Expiry date | Jul 28, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/393
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An image memory control device is disclosed by which high speed reading processing can be performed without causing a CPU of a computer to have a waiting time and without expanding the system scale. When the CPU tries to perform read access to an image memory, a CPU read mode signal is changed over and a first-in first-out memory controller delivers a read access request to a memory access controller irrespective of presence or absence of read access, and data read in from the image memory are stored into a FIFO memory under the control of the memory controller. Upon read accessing from the computer, the data are transferred from the first-in first-out memory, which assures higher speed operation. Where writing of video data and read/write access of the computer to the image memory are performed by a same system, the FIFO memory is used as a common buffer to them in a time dividing condition by changing over between them.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.