Method and apparatus for reducing power consumption in memory circuits
US5530676A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 1995 |
| Grant date | Jun 25, 1996 |
| Priority date | — |
| Expiry date | Jan 27, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock signal (202) is received, wherein the rising edge of the clock signal (202) controls an operation of a memory cell (224) of a memory circuit (200). Address information (204) is received and predecoded prior to the rising edge of the clock signal (202) to produce a row select signal (210). A control signal (201), which is received prior to the rising edge of the clock signal, determines whether the operation is a read operation or a write operation. If the operation is a write operation, new data information (218) is received a data delay after the rising edge of the clock signal (202); the row select signal (210) is delayed such that the memory cell (224) is selected at least a data delay after the rising edge of the clock signal (202); and the new data information (218) is written to the memory cell (224).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.