Hit enhancement circuit for page-table-look-aside-buffer
US5530823A · kind A · utility
27Cited by
20References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 12, 1992 |
| Grant date | Jun 25, 1996 |
| Priority date | — |
| Expiry date | May 12, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A virtual memory computing system is provided with a novel table-look-aside-buffer (TLB). The table-look-aside-buffer is located in cache memory and provides high speed verification that a page address being accessed by the instruction processor is present in the high speed mass storage unit (MSU) of the computer system. In the event of a page miss in the TLB, the control circuits associated with the TLB fetch a page descriptor and generate a translated real page address which is stored in the TLB in an invalidated (decelerated) or non-degraded and least recently used address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.