Data processor with branch target address cache and method of operation
US5530825A · kind A · utility
66Cited by
1References
4Claims
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Assignee
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Key dates
| Filing date | Apr 15, 1994 |
| Grant date | Jun 25, 1996 |
| Priority date | — |
| Expiry date | Apr 15, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processor (10) has a BTAC (48) storing a number of recently encountered fetch address-target address pairs. Each pair also includes an offset tag identifying which one of a plurality of instructions indexed by the fetch address generated the entry. A branch unit (20) generates an execution address that depends upon one of the plurality of instructions. After executing each instruction, the branch unit may delete an entry from the BTAC if the instruction's execution address differs from the target address and if the instruction is the same instruction which generated the BTAC entry initially.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.