Set-associative cache memory having an enhanced LRU replacement strategy
US5530834A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 1994 |
| Grant date | Jun 25, 1996 |
| Priority date | — |
| Expiry date | Mar 3, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0864
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory contains a number of RAMs. The RAMs are addressed by independent hashing functions, so as to access a set of locations, one in each RAM. If the required data item is resident in the addressed set, it is accessed. Otherwise, the least-recently used location in the set is selected for overwriting with data from main memory. The contents of the RAM location that is about to be overwritten are saved, and then used to access the memory again in order to address a further set of locations. If any of this further set of locations is less recently used than the saved contents, the saved contents are loaded back into that location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.