Method and apparatus for multiple memory bank selection
US5530836A · kind A · utility
77Cited by
13References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 12, 1994 |
| Grant date | Jun 25, 1996 |
| Priority date | — |
| Expiry date | Aug 12, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one aspect a memory bank selection system includes two asynchronous RAS pins and a single CAS pin, a switching circuit for each memory bank and a bank address decoder with an output to each switching circuit. The RAS pins are available to all of the switching circuits. A given switching circuit selects its associated bank if an active RAS signal is present and the bank address decoder output was sent thereto. The number of memory banks that can be simultaneously active directly depends on the number of RAS inputs. In another aspect, the number of CAS pins is equal to the number of asynchronous RAS pins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.