Address decoder with memory allocation for a micro-controller system
US5530840A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1993 |
| Grant date | Jun 25, 1996 |
| Priority date | — |
| Expiry date | Dec 9, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG07B2017/00395
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
The micro-controller system is comprised of a programmable microprocessor, a plurality of memory units having a plurality of addressable memory registers. The memory units are in bus communication with the programmable processor and an application specific integrated circuit. The application specific integrated circuit includes a circuit for dividing the memory units into a plurality of addressable regions in response to programming of the programmable microprocessor. The microprocessor is programmed such that the initial address for each of the regions is assigned by the most significant address bits, and the uppermost address for the region being programmably defined by an uppermost address for the respective region. The circuit includes a plurality of addressable registers. The microprocessor can address each of the circuit registers and write a respective uppermost address in a respective one of the registers, the respective address corresponding to uppermost addressable registers of the respective addressable regions of the memory units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.