Register allocation methods having upward pass for determining and propagating variable usage information and downward pass for binding; both passes utilizing interference graphs via coloring
US5530866A · kind A · utility
63Cited by
7References
34Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 13, 1994 |
| Grant date | Jun 25, 1996 |
| Priority date | — |
| Expiry date | Oct 13, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides methods for allocating physical registers within a compiler phase to achieve efficient operation of a target CPU. The methods of the present invention allocate variables between physical registers and memory to accommodate local as well as global code structure. Such methods facilitate the location of variables that are heavily accessed at a portion of the code in a physical register during the execution thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.