Method and apparatus for processing interruption
US5530873A · kind A · utility
81Cited by
4References
2Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 2, 1993 |
| Grant date | Jun 25, 1996 |
| Priority date | — |
| Expiry date | Aug 2, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/462
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Shadow registers for processing interruption are provided in a CPU. When the control shifts to interruption routine, the shadow registers are used for the interruption routine by changing the use of ordinary registers thereto, and the ordinary registers are prohibited to be used during a period of the interruption. Subsequently to the finish of the interruption, the ordinary registers are re-used without the necessity of the store and the re-store of the ordinary registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.