System and method for computer interface board identification by serially comparing identification address bits and asserting complementary logic patterns for each match
US5530895A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 25, 1993 |
| Grant date | Jun 25, 1996 |
| Priority date | — |
| Expiry date | Feb 25, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/177
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for automatically identifying and configuring interface boards connected to a computer bus is disclosed. Each interface board contains a pair of interface ports that can be addressed by the system and a unique identification address. The interface boards are instructed to serially read the identification address and place a logic 10 in the two least significant bits of the data bus if the first data bit is a logic one. The serial read instruction is performed twice for each data bit in the identification address with a logic 01 data pattern placed on the data bus for the second serial read to assure that a floating data bus is not causing false readings. If no interface board responds to any particular read identification instruction, the system assigns a logic zero for that particular bit of the identification address. Any interface board not having a logic one for a particular first data bit in the identification automatically places itself in a disabled state if the first and second serial read instructions indicate that another interface board did have a logic one for that particular data bit of the identification address. By the time that the system has rea…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.