Cache coherent multiprocessing computer system with reduced power operating features
US5530932A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1994 |
| Grant date | Jun 25, 1996 |
| Priority date | — |
| Expiry date | Dec 23, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessing system maintains cache coherency during a reduced power mode of operation. The multiprocessing system has a first and a second processor coupled to the bus to perform data transactions with the main memory. During the reduced power mode of operation, the internal clock signal of the second processor is decoupled from a portion of the internal logic of the second processor while remaining coupled to a portion of the internal logic of the second processor that is used to monitor and respond to the traffic on the external bus to maintain cache coherency. During the reduced power mode of operation, the second processor continues to perform snoop and write-back processes to maintain a cache coherent multiprocessing system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.