Method of forming a three dimensional high performance interconnection package
US5531022A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 1994 |
| Grant date | Jul 2, 1996 |
| Priority date | — |
| Expiry date | Sep 2, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/53174
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention is directed to a structure for packaging electronic devices, such as semiconductor chips, in a three dimensional structure which permits electrical signals to propagate both horizontally and vertically. The structure is formed from a plurality of assemblies. Each assembly is formed from a substrate having disposed on at least one surface a plurality of electronic devices. Each assembly is disposed in a stack of adjacent assemblies. Between adjacent assemblies there is an electrical interconnection means electrically interconnecting each assembly. The electrical interconnection means is formed from an elastomeric interposer. The elastomeric interposer is formed from an elastomeric material having a plurality of electrical conductors extending therethrough, either in a clustered or un-clustered arrangement. The electrical interconnection means is fabricated having a plurality of apertures extending therethrough. The array of apertures corresponds to the array of electronic devices on the substrates. The aperture and electrical interconnection means is disposed over the array of electronic devices so that the electrical interconnection means is between adjacent e…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.