Random access memory redundancy circuit employing fusible links
US5532966A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 1995 |
| Grant date | Jul 2, 1996 |
| Priority date | — |
| Expiry date | Jun 13, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/832
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor random access memory (RAM) is disclosed having a number of array blocks (14), each array block (14) including standard rows, standard columns, redundant rows (24) and redundant columns (26). A row redundancy circuit (44) is provided for each array block that includes a single row fuse bank (28). Within the row fuse bank (28) are row disable fuses (42) and redundant row fuses (54) interspersed at regular intervals between the row disable fuses (42). Each row disable fuse (42) disables a standard row segment (32) when opened. A redundant row segment (46) is driven according to the combination of opened redundant row fuses (54). A column redundancy circuit (62) includes a number of column fuses (64) disposed in a column fuse bank (30). Redundant columns (26) are enabled by opening selected ones of the column fuses (64). If a redundant column (26) is driven the remaining standard columns of its associated array block (14) are disabled. Column fuse banks (30) are commonly aligned with row fuse banks (28) along fuse axes (16 and 18).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.