Latency error detection circuit for a measurement system
US5533037A · kind A · utility
12Cited by
6References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 24, 1994 |
| Grant date | Jul 2, 1996 |
| Priority date | — |
| Expiry date | May 24, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0757
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A latency error detection circuit including two cascaded latches receiving a clock signal from a measuring system upon the occurrence of an event and correspondingly asserting a bit to a processing system, and a circuit for clearing the first latch after the processing system acknowledges detecting the bit being asserted. If the second latch is clocked before the first latch is cleared, the second latch sets an error bit indicating a latency error condition. The processor system monitors the error bit to determine whether a latency error has occurred.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.