Self-clocking pipeline register
US5534796A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 21, 1995 |
| Grant date | Jul 9, 1996 |
| Priority date | — |
| Expiry date | Apr 21, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A control module for controlling a data register, a self-clocking data register controlled by such a module and a pipeline of self-clocked pipeline registers. The localized control module includes a flip-flop for indicating whether the data register being controlled is occupied or vacant. Each module includes state machine logic for generating an enable output to the pipeline register when the flip-flop indicates the register was vacant and a load signal indicating data is available for loading into the register has been received. The localized control may be further modified to provide look-ahead in which an enable output is also generated when a load signal has been received and an unload signal has been received.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.