Synchronized clock generating apparatus
US5534805A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 1995 |
| Grant date | Jul 9, 1996 |
| Priority date | — |
| Expiry date | May 24, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00234
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A synchronized clock generating apparatus includes a delayed clock generating circuit including a plurality of serially connected delaying elements for generating delayed clock signals delayed successively to an incoming basic clock signal. A plurality of storage elements store therein a predetermined level in response to transitions occurring in associated ones of the basic and delayed clock signals after an asynchronous trigger signal is applied thereto. A clock selection logic circuit is controlled by the output signal from the storage elements for detecting the clock signal transition occurring closest in time to the application of the asynchronous trigger signal, and for selecting a desired one of the clock signals based on the result of the detection, as a synchronized clock input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.