Multiple key array
US5534860A · kind A · utility
Inventors
Key dates
| Filing date | May 2, 1994 |
| Grant date | Jul 9, 1996 |
| Priority date | — |
| Expiry date | May 2, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M11/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus for and method of scanning a key array (101-116) uses two or three scan lines (134 and 135 or 308, 309, and 310), thereby limiting the need for an excessive number of input/output lines of a processor (136). A separate resistor ladder (301,302, 303) is provided for each dimension of keys, including row, column, and/or matrix. A minimal number of parts is also required to implement the resistor ladder (301,302, 303). A reference conductor (311), a row conductor (312), a column conductor (313), and, if desired, a matrix conductor (314) each run under each key, such that when a different key is depressed, a unique combination of voltages appears at the scan lines (134 and 135 or 308, 309, and 310) for the resistor ladders (301, 302, 303).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.