ESD protection circuit and method for BICMOS devices
US5535086A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 22, 1994 |
| Grant date | Jul 9, 1996 |
| Priority date | — |
| Expiry date | Sep 22, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/046
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An ESD protection circuit for a BICMOS IC device protects NMOS transistors (Q2) of internal CMOS gates (G2) from ESD events at a high potential power rail (VCC). Specifically the ESD protection circuit protects NMOS pulldown transistors coupled between a pullup bipolar emitter follower transistor (Q5) and the low potential power rail (GND). A PMOS current control transistor (QPESD) is coupled with primary current path between the high potential power rail (VCC) and the bipolar emitter follower transistor (Q5) for controlling current flow through the emitter follower transistor. An RC time constant circuit (R10,C1) is coupled between the high potential power rail (VCC) and low potential power rail (GND). The RC time constant circuit is constructed with a time constant for following power up events but not for following the faster ESD events at the high potential power rail. An inverting gate (G2A) is coupled between the control gate node of the PMOS current control transistor (QPESD) and the RC time constant circuit (R10,C1) for turning off the PMOS current control transistor (QPESD) during an ESD event at the high potential power rail. The PMOS current control transistor (QPESD) th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.