Method and apparatus for the verification and testing of electrical circuits
US5535223A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 1995 |
| Grant date | Jul 9, 1996 |
| Priority date | — |
| Expiry date | Feb 17, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The system of the present invention provides for the verification and testing of electrical circuits and the generation of the information necessary to interface with computer aided testing equipment to physically test the fabricated circuits. The verification of the circuit is divided into two portions, functional verification and timing verification. Information generated during the verification process using the separate functional and timing verification information are then combined into a core structure from which test vectors are generated in a format compatible with a circuit testing apparatus which physically tests the fabricated circuit. In this format, unit delays previously employed to perform the timing tests are adjusted according to the timing specifications of the components to comply with the setup and hold times specified. Using this process, the test vectors required by the physical test apparatus to physically test a fabricated circuit are generated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.