VLSI architectures for polygon recognition
US5535292A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1993 |
| Grant date | Jul 9, 1996 |
| Priority date | — |
| Expiry date | Dec 30, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06V10/757
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A VLSI structure and method for polygon recognition that identifies an unknown two dimensional contour as corresponding to one or more of a plurality of known two dimensional contours. The VLSI architecture comprises a systolic processing system comprising a plurality of matrix element processing elements (MEPEs), and an array of feasible match processing elements (FMPEs) interconnected with selected MEPEs and with each other in a predetermined configuration. The plurality of MEPEs receive inputs comprising pairs of edge length ratios and corresponding threshold values for consecutive edges of the unknown contour and for each of the known polygon contours. Each MEPE (i) receives edge length ratios and threshold values for a pair of edges of the unknown contour and a known polygon contour, (ii) determines a dissimilarity value for the pair of edges, and (iii) directs this value to a selected FMPE of the array. The dissimilarity value is determined using the absolute differences between respective edge length ratios and threshold values for the pair of edges. The array of FMPEs determines feasible matches between pairs of consecutive edges of the unknown contour and the known polygon…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.