Address generating circuit for data compression
US5535353A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 1993 |
| Grant date | Jul 9, 1996 |
| Priority date | — |
| Expiry date | Jun 8, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An address generating circuit for data compression includes an X-address generating circuit (10), a Y-address generating circuit (20), an XY-address generation control circuit (30) and a defect analyzing memory (40). Each of the circuits (10) and (20) include a flip-flop (3A), a selector (2), an upcounter (4), an adder (5), a down-counter (6) and a comparator (1). The control circuit (30) receives address end signals J and address carry signals L from the circuits (10) and (20) to control the circuits (10) and (20). The memory (40) has address signals K from the circuits (10) and (20). Processing time required to check defects of a large capacity memory device is reduced because address generators are provided not only on the X-address side but also on the Y-address side and the compression ratio is set in the address generating circuit, thereby accelerating the defect analysis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.