Microsequencer bus controller system
US5535405A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1993 |
| Grant date | Jul 9, 1996 |
| Priority date | — |
| Expiry date | Dec 23, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1625
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microsequencer bus controller system provides a flexible and efficient mechanism for controlling multiple gate arrays called stations embedded within a larger computer system. A control store memory, loaded at system initialization time, holds fixed-length instructions simultaneously executed by dual reduced instruction set (RISC) microprocessors which interface with the multiple stations over a bi-directional bus. The master microprocessor compares the result of the processing of each instruction with the slave microprocessor's result to detect any differences, thereby minimizing error latency. Master and slave microprocessors each control half of the stations on the bus. Data widths of 32-bit and 36-bit words are supported by the microprocessors, bus, and stations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.