Secondary data transfer mechanism between coprocessor and memory in multi-processor computer system
US5535414A · kind A · utility
13Cited by
31References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 13, 1992 |
| Grant date | Jul 9, 1996 |
| Priority date | — |
| Expiry date | Nov 13, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/423
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system having a CPU, a memory subcircuit, a peripheral subcircuit, a primary SCSI controller, which generates a SCSI bus, a coprocessor, and a secondary SCSI controller, also attached to the SCSI bus. These components are operatively connected in such a way that the coprocessor can access the SCSI bus through the secondary SCSI controller without interfering with the CPU's ability either to run a program from the memory subcircuit or to receive data and control input from the peripheral subcircuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.