Method for protecting an ASIC by resetting it after a predetermined time period
US5537055A · kind A · utility
10Cited by
4References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1994 |
| Grant date | Jul 16, 1996 |
| Priority date | — |
| Expiry date | Jun 30, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/003
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A design protection circuit for a logic circuit comprised of a counter for receiving clock pulses with the logic circuit and apparatus for resetting the logic circuit upon the counter counting a predetermined number of clock pulses, the predetermined number being higher than a highest number of clock pulses required by the logic circuit for carrying out a simulated logical function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.