Shared memory for split-panel LCD display systems
US5537128A · kind A · utility
88Cited by
14References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 4, 1993 |
| Grant date | Jul 16, 1996 |
| Priority date | — |
| Expiry date | Aug 4, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G3/2018
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The video memory and the half-frame buffer frame accelerator of a dual scan LCD display are integral in a single memory device. Flat-panel read and write cycles to the frame accelerator designed area inside the memory are optimized in order to minimize memory bandwidth requirements. Extra memory space in the memory device may be used to buffer multiple half-frames of shaded data in such a manner as to save a considerable amount of power in the LCD display graphics system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.