Low pin count-wide memory devices and systems and methods using the same
US5537353A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 1995 |
| Grant date | Jul 16, 1996 |
| Priority date | — |
| Expiry date | Aug 31, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/066
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device 200 which includes a multiplexed address/data input/output 230. Circuitry 200 is based around an array 201 of memory cells and includes circuitry 202, 204 for addressing at least one of the cells in the array in response to at least one address bit and circuitry 208, 210, 211, 212 for exchanging data with an addressed one of the cells. Memory device 200 also includes control circuitry 206 operable to pass an address bit presented at the multiplexed input/output to the circuitry for addressing during a first time period and allow for the exchange of data between the circuitry for exchanging and multiplexed input/output during a second time period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.