Interleaved memory wherein plural memory means comprising plural banks output data simultaneously while a control unit sequences the addresses in ascending and descending directions
US5537577A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 1993 |
| Grant date | Jul 16, 1996 |
| Priority date | — |
| Expiry date | May 6, 2013 |
Classification
- Technology area (CPC F)Mechanical Engineering; Lighting; Heating
- CPC primaryF02B2075/025
- WIPO fieldEngines, pumps, turbines
- WIPO sectorMechanical engineering
Abstract
An interleaving memory system having a first memory device including a 0-bank and a 1-bank for simultaneously outputting data at even-numbered addresses from the 0-bank and data at odd-numbered addresses from the 1-bank, a second memory device including a 0-bank and a 1-bank for simultaneously outputting data at even-numbered addresses from the 0-bank and data at odd-numbered addresses from the 1-bank, and a holding device for holding data from one of the banks of one of the first memory device and the second memory device to delay an output of the data for 1/2 cycle time for sequential addressing. A controller controls first and second selection devices wherein the 0-bank and the 1-bank are alternatively selected when data is outputted either in an ascending order of consecutive addresses from the even-numbered addresses in the first or second memory devices, or in a descending order of consecutive addresses from the odd-numbered addresses in the first or second memory devices. Also, the first holding device and a bank whose output is not held by the first holding device are alternatively selected when data is outputted either in a descending order of consecutive addresses from th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.