Redundant load elimination on optimizing compilers
US5537620A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 16, 1994 |
| Grant date | Jul 16, 1996 |
| Priority date | — |
| Expiry date | Sep 16, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/443
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for eliminating redundant loads in an optimizing compiler is provided. When a LOAD and memory operation occur in an iterative loop structure having an induction variable, the method determines if redundant load elimination optimization may be performed by performing the steps of: creating a symbolic address for a LOAD operation, where the LOAD operation follows a memory operation, creating a symbolic address for the memory operation which precedes the LOAD, and subtracting the LOAD symbolic address from the memory operation symbolic address to generate a difference. If the difference is a constant which is divisible by the increment of the induction variable, the method eliminates the LOAD instruction for each increment of the loop and includes an instruction to copy the value of the memory operation to a register, and further includes an instruction to move the copied value from the register to the target of the load. An additional feature of the invention includes the step of, if the difference is a constant which is divisible by a multiple of the increment of the induction variable, wherein the multiple is greater than one, including additional instructions to copy the …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.