Decoder for single cycle decoding of single prefixes in variable length instructions
US5537629A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 1994 |
| Grant date | Jul 16, 1996 |
| Priority date | — |
| Expiry date | Mar 1, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30149
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A prefix decoder for decoding a plurality of prefixes of a variable length instruction code, in order to supply multiple prefix vectors to a multiple instruction decoder without incurring a one clock penalty. The parallel prefix decoder includes a plurality of prefix decoders, each coupled to receive an instruction byte from an instruction buffer, and in response thereto to supply a prefix vector that includes coded prefix information in a format that is easy to use by subsequent decoder logic. A multiplexer receives the plurality of prefix vectors, and if a steered macroinstruction has a single prefix byte, then a control circuit selects the prefix vector to supply to the macroinstruction decoder. If multiple macroinstructions are steered to multiple macroinstruction decoders, then a prefix vector can be supplied to each decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.