Microcontroller having selectable bus timing modes based on primary and secondary clocks for controlling the exchange of data with memory
US5537660A · kind A · utility
9Cited by
15References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 17, 1994 |
| Grant date | Jul 16, 1996 |
| Priority date | — |
| Expiry date | Nov 17, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit microcontroller with improved system bus timing modes that allow higher speed operation when accessing external memory. The improved system bus timing modes are generated by using the edges of a higher frequency secondary clock to trigger system bus timing events instead of using the edges of the phase clock. This can be done without major redesign using combinational logic because the phase clock and the higher frequency secondary clock are substantially in-phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.