Methods and apparatus for generating I/O recovery delays in a computer system
US5537664A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 1996 |
| Grant date | Jul 16, 1996 |
| Priority date | — |
| Expiry date | Jan 4, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system comprising programmable I/O recovery includes a device selection unit, programmable I/O recovery time registers, and a decrementer for specifying I/O recovery times for a plurality of I/O peripheral components. The programmable I/O recovery time registers contain time values, and the time values are programmable by the user of the computer system. The computer system interfaces the I/O peripheral components on an external bus through a plurality of bus cycle signals generated by cycle generation logic. For each I/O bus cycle on the external bus, the device selection unit identifies the I/O device involved in the I/O bus cycle. The device selection unit selects a time value from the programmable I/O recovery time registers corresponding to the I/O device identified, and loads the time value selected in the decrementer. Upon termination of the bus cycle, the device selection unit generates a cycle start signal to enable counting in the decrementer. The decrementer begins to count down from the time value loaded, and when the decrementer reaches a terminal count, a ready signal is generated. The ready signal enables the cycle generation logic to generate a successive…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.