Method of making a narrow gate electrode for a field effect transistor
US5538910A · kind A · utility
13Cited by
2References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 25, 1995 |
| Grant date | Jul 23, 1996 |
| Priority date | — |
| Expiry date | Jan 25, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28593
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of producing a field effect transistor that includes forming a step in a compound semiconductor substrate, forming a first insulating side wall at the step, forming an etch blocking layer on the substrate, removing the first insulating side wall, and etching the substrate not protected by the etch blocking layer to produce a recess. Subsequently, a second insulating side wall is formed at the sides of the recess, a refractory metal and a low resistance metal are sequentially deposited and formed as a gate electrode, and finally, source and drain electrodes are formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.