Semiconductor memory device and method for reading and writing data therein
US5539691A · kind A · utility
18Cited by
5References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 5, 1995 |
| Grant date | Jul 23, 1996 |
| Priority date | — |
| Expiry date | Jun 5, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1051
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An NAND gate for outputting an output establishment detection signal in response to the fact that a complementary output of a latch type sense amplifier has been established is provided. When a tristate buffer is activated by signal, a word line which has been in a selected state is rendered non-selected state. Accordingly, current can be prevented from leaking from a power supply line to a ground line in tristate buffer. In addition, column current Ic flowing through memory cells can be minimized in response to the fact that word line has been set to a selected state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.