Asynchronous interface between parallel processor nodes
US5539739A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 1994 |
| Grant date | Jul 23, 1996 |
| Priority date | — |
| Expiry date | Sep 29, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17381
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An asynchronous interface enabling a processor node operating at a first clocking frequency to transfer and receive information from a communications network operating at a second clocking frequency. The asynchronous interface comprises an input synchronizer and an output synchronizer. The input synchronizer asynchronously receives a first plurality of information packets from the processor node and synchronously transfers the first plurality of information packets into the communications network. The output synchronizer, however, synchronously receives a second plurality of information packets from the communications network and asynchronously transfers the second plurality of information packets into the processor node. Both the input and output synchronizers are coupled between the communications network and the processor node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.