Jitter/wander reduction circuit for pulse-stuffed, synchronized digital communications
US5539785A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 1994 |
| Grant date | Jul 23, 1996 |
| Priority date | — |
| Expiry date | Jul 27, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/073
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A jitter/wander reduction circuit is provided for a desynchronizer deriving an output clock signal from an independent clock signal and phase adjustment signals. Phase adjustment signals relate to a deviation of the independent clock signal from an input clock signal. The circuit includes a frequency offset estimation circuit receiving phase adjustment signals and providing a frequency offset estimation signal. A phase controller receives the frequency offset estimation signal, provides a feedback signal to the frequency offset estimation circuit, and provides a phase difference signal. A clock generator circuit receives the independent clock signal and the phase difference signal. The independent clock signal is adjusted based on the phase difference signal to provide an output clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.