System and method for processing external conditional branch instructions
US5539888A · kind A · utility
8Cited by
16References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 6, 1995 |
| Grant date | Jul 23, 1996 |
| Priority date | — |
| Expiry date | Jan 6, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3877
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for executing conditional branch instructions by a data processing system containing a programmable microprocessor and multiple VLSI gate arrays connected by a bi-directional bus, whereby a branch condition is obtained from a storage location resident on a VLSI gate array executing asynchronous and external to the microprocessor. The branch condition is fetched and evaluated in parallel with the fetching of the branch target address and the incrementing of the program counter. The microprocessor changes instruction sequence control depending on the results of the branch condition evaluation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.