Integrated compact capacitor-resistor/inductor configuration

US5541442A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Richard F. Keil · Jonesville, US
• Ram Kelkar · South Burlington, US
• Ilya I. Novof · South Burlington, US
• Jeffery H. Oppold · South Burlington, US
• Kenneth Dean Short · South Burlington, US
• Stephen D. Wyatt · Jericho, US

Key dates

• Filing date: Aug 31, 1994
• Grant date: Jul 30, 1996
• Expiry date: Aug 31, 2014

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/00

Abstract

An improved configuration of a capacitor formed with FET technology and a resistor and/or conductor is provided. In this configuration a capacitor is formed in which the diffusion zone of the substrate is used as one plate of the capacitor and what would normally be the gate electrode of an FET is used as the other plate of the capacitor, with the two plates being separated by a conventional thin dielectric gate oxide layer. An insulator, such as silicon dioxide overlays the gate electrode, and electrical connections to the gate electrode and diffusion zone are made through the insulator to allow the two plates of the capacitor to be connected to various devices or components as required. The top surface of this insulation layer is also used to form metal resistors. Depending on the value of required resistance, a second insulating layer may be used and a second level of metal used to connect segments of the resistors formed on the first layer of metal to form a longer resistor. This second layer of metal may also be used to form inductors. Moreover both inductors and resistors can be formed; however this may require a third layer of metal for connection purposes.