Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks
US5541530A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 1995 |
| Grant date | Jul 30, 1996 |
| Priority date | — |
| Expiry date | May 17, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/04
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic array integrated circuit device has logic regions grouped in blocks, which are in turn grouped in super-blocks. The super-blocks are disposed on the device in a two-dimensional array of intersecting rows and columns. Global conductors are associated with each row and column. Super-block feeding conductors associated with each super-block feed signals from the global conductors to any logic region in the super-block. Local feedback conductors feed back logic region output signals to all logic regions in a block. The super-block feeding conductors are also used to interconnect the logic regions in a super-block so that the global conductors do not have to be used for that purpose.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.