Multi-phased pipeland analog to digital converter
US5541602A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 1995 |
| Grant date | Jul 30, 1996 |
| Priority date | — |
| Expiry date | May 26, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/44
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog to digital converter stage that has a very short sampling phase settling time requirement is used in a multistage pipelined analog to digital converter with a novel clocking design. Each clock period has a sampling phase and a hold phase. According to a first aspect, the sampling phase of each clock cycle is much shorter than the hold phase. This takes advantage of the reduced sampling phase settling time requirement of the analog to digital converter stage according to the present invention, and also allows a relatively longer hold phase during each clock cycle. The analog to digital converter stage according to the present invention is implemented with an operational amplifier such that during the sampling phase, the operational amplifier does not have to settle in order for correct sampling to occur, whereas operational amplifier settling is required during the hold phase. According to a second aspect, several clocks are cyclicly recirculated among the stages of a pipelined analog to digital converter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.