Circuit for freezing the data in an interface buffer
US5541932A · kind A · utility
8Cited by
2References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 3, 1995 |
| Grant date | Jul 30, 1996 |
| Priority date | — |
| Expiry date | Feb 3, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for enabling data transfer between one data bus connected to a number of devices, such as accelerator cards, and a second data bus, such as one found in a computer. The two data busses are connected by a number of FIFO buffers, and an arbitrator selects a source and destination for each packet. The circuit allows the computer to freeze the data in any or all buffers so that it can be inspected and changed if necessary, but only after the entire current packet for the selected buffer or buffers has been transferred.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.