Apparatus, systems and methods for isolating faults during data transmission using parity
US5541934A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 1995 |
| Grant date | Jul 30, 1996 |
| Priority date | — |
| Expiry date | Oct 19, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuitry 300 is disclosed for isolating faults in a path 304 transmitting data words each having at least one data bit and at least one parity bit. Circuitry 300 includes a plurality of exclusive-OR gates 303 each having a first input coupled to the data path 304 for receiving a bit of a one of the data words being transmitted along path 304. A plurality of multiplexers 305 are also provided, each multiplexer 305 including a first input coupled to an output of a corresponding one of the exclusive-OR gates 303 and a control signal input for receiving a control signal. A plurality of registers 306 have an input coupled to an output of a corresponding one of the multiplexers 305 and an output coupled to a second input of a corresponding one of the exclusive-OR gates 303 and a second input of the corresponding one of the multiplexers 305. Each multiplexer 305 is operable to pass a bit presented at the output of the corresponding exclusive-OR gate 305 to the corresponding register 306 in response to a first state of the control signal and pass a bit presented at the output of the corresponding register 306 to the input of the corresponding register 306 in response to a second state of …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.