Parallel processor system with highly flexible local control capability, including selective inversion of instruction signal and control of bit shift amount
US5542074A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 1992 |
| Grant date | Jul 30, 1996 |
| Priority date | — |
| Expiry date | Oct 22, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8015
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel processor system which operates in a single-instruction multiple-data mode has a highly flexible local control capability for enabling the system to operate fast. The system contains an array of processing elements or PEs (12.sub.1 -12.sub.N) that process respective sets of data according to instructions supplied from a global control unit (20). Each instruction is furnished simultaneously to all the PEs. One local control feature (52) entails selectively inverting certain instruction signals according to a data-dependent signal. Another local control feature (48) involves controlling the amount of a bit shift in a barrel shifter (98) according to a data-dependent signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.