Process and structure for measuring the planarity degree of a dielectric layer in an integrated circuit and integrated circuit including means for performing said process
US5543633A · kind A · utility
15Cited by
3References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 15, 1993 |
| Grant date | Aug 6, 1996 |
| Priority date | — |
| Expiry date | Jul 15, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01B7/345
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for measuring the degree of planarity in an integrated circuit includes depositing, onto a dielectric layer to be measured for planarity, a predetermined measure path of a conductive film and measuring the electric resistance of said measure path. The resistance of such a measure path is minimal where the surface on which it has been deposited is perfectly planar, and increases with the surface deviation from perfect planarity. An integrated circuit containing a measurement portion of conductive film and a reference portion of conductive film is described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.